The present invention relates generally to a clock/buffer network in an integrated circuit device. More specifically, the invention relates to test signal routing in a device with a pre-built network in a non-customizable metal layer and an auto-routing network in a customizable metal layer.
Integrated circuit devices are used in a wide array of applications. To verify the quality of these devices, numerous tests can be carried out. Each device can be put through a rigorous industry standard test methodology to verify the quality of the device. Different test signals are typically controlled by different test pins and all these signals are routed to different parts of the integrated circuit to fully test the functionality of the circuit. As such, test signals need to be routed to different blocks in the integrated circuit to test the functionality of each logic block in an integrated circuit.
However, intensive test signal routing may cause congestion in the device, especially if the device is configured for a fairly complex application. Test signals generally come from test pins or I/O pins. As devices become smaller with more complex circuitry to support a wide variety of features, routing test signals in these devices has become more challenging. In other words, routing has become more complicated because the routing area has shrunk while the number of test signals has increased.
Furthermore, in some devices, test signal routing cannot be predetermined because resource usage varies from design to design. It is difficult to build a fully independent routing track as each unique design will invariably need a different routing track. Therefore, high-fanout test signal routing needs to be built fully in the customizable layer of such devices, e.g., the place and route layer, as every unique design will require a different test signal routing track. However, this may cause routing congestion because these high-fanout test signals may use up routing tracks that can otherwise be used for routing other design signals.
Therefore, it is highly advantageous to have an apparatus and method that can alleviate routing congestion in a customizable layer without impacting the size of the die. It is also advantageous to have a pre-built network in a base layer that interconnects with logic elements in the customizable layer to ease the congestion in the place and route layer. It is further desirable to have a pre-built or pre-defined network with buffers placed at strategic locations in the base layer because such a network can provide a deterministic timing model.